Self-organizing control

ABSTRACT

This disclosure relates to a self-organizing control system requiring minimum information storage capable of control of a plant by combining statistical decision theory to determine the true instantaneous plant performance, prediction theory to determine the performance trend, and rapid trial generation to ascertain what must be done to improve the performance trend. This is provided by on-line sampling and changing of system operation. The disclosure also includes performance assessment units and a probability state variable unit as subcombinations for carrying out the control operation.

United States Patent Barron 1 Oct. 10, 1972 1 SELF-ORGANIZING CONTROL 3,374,469 3/1968 Connelly ..340/ 172.5 '72 Inventor: R0 er L. Barron B k V Gerhardt et al. l 1 g e a 3,341,823 9/1967 Connelly ..340/172.5 Asslgneel Adaptromcs, McLean, 3,446,946 5/1969 Andeen ..235/150.1

22 Filed: Dec. 23 1968 1 Primary ExaminerGareth D. Shaw [21] Appl. NO- 8 58 Attorney-Jay M. Cantor Related U.S. Application Data 57] I ABSTRACT [601 El 2 i gd g p This disclosure relates to a self-organizing control N g i gg 0 system requiring minimum information storage capable of control of a plant by combining statistical decision theory to determine the true instantaneous plant C l IIIIIIIIIIIIIIIIIIIII performance, prediction theory to determine the per- 58] d H72 5' 233/157 150 1 formance trend, and rapid trial generation to ascertain le 0 c 5 what must be done to improve the performance trend. This is provided by on-line sampling and changing of system operation. The disclosure also includes per- [56] References Clted formance assessment units and a probability state vari- UNITED STATES PATENTS able unit as subcombinations for carrying out the control operat1on. 3,097,349 7/1963 Putzrath et al. ..340/l72.5 3,222,650 12/l965 Lazarus ..340/l72.5 26 Claims, 15 Drawing Figures CUMMI/VD Ill/P07 4 g3)?! J'E'LF-Ofi4/Y/Z/IV6' CMTOLLEE MTQL D/FFAENT/JL 523$? Ase/06 mm: y ag a man/4L mazea I r a AMPL/F/'E nmwnEA/r 2o MG/c 7 Pin/V7 awa 0 YE/KYO? PATENIEDum 10 I972 SHEET DSUF 11 ATTOeA/EYS.

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SELF-ORGANIZING CONTROL DISCLOSURE OF THE INVENTION This application is a division of Ser. No. 565,162 filed July 14, 1966, now US Pat. No. 3,460,096, which is a continuation-in-part of application, Ser. No. 535,551, filed Mar. 18, 1966, both entitled Self-Organizing Control System.

This invention relates to self-organizing control systems and, more particularly, to a high-speed self-organizing control system requiring a minimum of information storage. The disclosure in this application describes a self-organizing control system that uses only a short term record of its control signal experiments and requires essentially no memory for the sequences of system performance values which result during controller operation. Successful high-speed selforganization is accomplished by the system via generation of internal signals representing, at any point in time:( 1) polarity polarities of recent change or changes control signals and (2) instantaneous control system performance.

A main object of the invention is to provide a novel and improved self-organizing control system wherein predicted system performance is evaluated on-line either continuously or periodically to modify the course of action pursued by the self-organizing elements of the system.

A further object of the invention is to provide novel and improved self-organizing control systems which employ a performance assessment stage which is highly effective in a wide range of control system applications, the performance assessment stage being of a nature to be incorporated in a self-contained module which is compatible with a variety of designs of other stages of the over-all system, the module being applicable to many areas directed to problems of a specific type, such as stabilization, control, and dynamic process identification.

A further object of the invention is to provide an improved seIf-organizing control system employing a novel and efficient probability state variable conditioning logic module, namely, a device which changes its output state in response to a conditioning signal from a performance assessment module, said conditioning logic module basing each change of state on both the level of the received conditioning signal and the internal memory record of that output state change which (acting through the environment) resulted in the conditioning signal, whereby the ability of the conditioning logic module to associate cause and effect, basing its decisions on accumulated statistical evidence conceming the presence of predicted results of its past actions, permits realization of effective self-organizing control actions, the conditioning logic module being applicable to a wide range of situations, from those involving linear, single variable control problems to situations involving multiple, coupled variables and time-varying, nonlinear dynamic environments, and being applicable to many problems of a specific type, such as stabilization, control, and dynamic process identification, as above-mentioned.

A further object of the invention is to provide a novel and improved self-organizing control system employing a dynamic performance assessment means which can process information pertaining to all significant variables of the controlled process, thereby providing computation of a single, unified performance measure which is a function of all significant variables of the controlled process, said unified performance measure being used with multiple conditioning logic modules to generate control action signals for multiple actuation de-vices, the conditioning logic modules being at least equal in number to the number of such actuation devices, and probability state variable conditioning logic being used in said conditioning logic modules to obtain an efficient search within the multivariable parameter space represented by said multiple control action signals, thus producing effective control actions capable of involving all actuation devices simultaneously when required.

A further object of the invention is to provide an improved self-organizing control system which produces satisfactory control without the usual reliance on a priori data during design and operation of the system, said a priori data pertaining to the characteristics of the controlled plant and the environment in which it operates, this freedom from reliance on a priori data being accomplished without generating limit-cycle oscillations of the controlled variable, elimination of said limit-cycle oscillations being a result of the random output sequences produced by the probability state variable conditioning logic.

A still further object of the invention is to provide an improved self-organizing control system in which the outputs of multiple, parallel, probability state variable conditioning logic modules are summed algebraically to provide with high reliability the controlsignal for each channel of actuation, said high reliability being a consequence of the tolerance of the self-organizing controller in this parallel configuration for malfunctions or failures of some but not all of the parallel connected conditioning logic modules, said configuration also providing improved quality of performance of the self-organizing controller by virtue of the additional dynamic range available in the regulating control signal, which additional dynamic range is afforded by the parallel connection of conditioning logic modules.

A yet further object of the invention is to provide an improved self-organizing control system in which the quality of control is not critically sensitive to the amplitudes or frequencies of noise components present in the signals from the sensors, this relative insensitivity to noise being the result of statistical decision processes employed by the probability state variable conditioning logic.

Detailed background discussion of the theory and application of self-organizing control systems would be beyond the scope of this patent application disclosure. A survey of the underlying theory and practice as relates to the self-organizing control system disclosed in this application is contained in the technical paper Self-Organizing and Learning Control Systems by Roger L. Barron, published in conjunction with the 1966 Bionics Symposium sponsored by the Air Force Avionics Laboratory, Research and Technology Division, Air Force Systems Command, United States Air Force, Wright-Patterson Air Force Base, Ohio which symposium was conducted May 2 -5, 1966, in Dayton, Ohio. Said paper presents, in addition to theoretical matters, the results of an investigation of the application of the self-organizing control system disclosed in this application to pitch-rate and normal-acceleration control of a high-performance aircraft. Reference is also made in the said paper to single-axis and multipleaxis control of orbiting spacecraft; throttle control for aircraft landing approaches; and control of large, flexible space launch vehicles.

Further objects and advantages of the invention will become apparent from the following description and claims, and from the accompanying drawings, wherein:

FIG. 1 is a block diagram of a generalized typical self-organizing control system employing a novel and improved performance assessment stage in conjunction with a novel and improved conditioning logic stage constructed in accordance with the present invention.

FIG. 2 is a block diagram of the novel and improved conditioning logic stage, .or probability state variable (PSV) conditioning logic, employed in the self-organizing control system of FIG. 1.

FIG. 3 is a block diagram of a first type of novel and improved performance assessment stage which may be employed in the self-organizing control system of FIG. 1.

FIG. 4 is a block diagram of a second type of novel and improved performance assessment stage which may be employed in the self-organizing control system of FIG. 1.

FIG. 5 is a functional diagram detailing the operations which comprise the PSV conditioning logic of FIG. 2.

FIG. 6 is a functional diagram detailing the operations which comprise the first type of performance assessment illustrated in FIG. 3.

FIG. 7 is a functional diagram detailing the operations which comprise the second type of performance assessment illustrated in FIG. 4.

FIG. 8 is a functional schematic detailing the generalized electrical circuit of the P register, P-register control logic, and digitaI-to-analog conversion of the P-register contents as employed in the PSV conditioning logic of FIGS. 2 and 5.

FIG. 9 is a functional schematic detailing the generalized electrical circuit of the statistical source as employed in the PSV conditioning logic of FIGS. 2 and 5.

FIG 10 is a functional schematic detailing the generalized electrical circuit of the U register, U-register control logic, and digital-to-analog conversion of the U-register contents as employed in the PSV conditioning logic of FIGS. 2 and 5.

FIG. 11 is a functional schematic detailing the generalized electrical circuit of the sign Ay.(t) memory as employed in the PSV conditioning logic of FIGS. 2 and 5.

FIG. 12 is a functional schematic detailing the generalized electrical circuit of the logic'time base as employed in the PSV conditioning logic of FIGS. 2 and 5.

FIG. 13 is a functional schematic detailing the generalized electrical circuit of the first type of performance assessment illustrated in FIGS. 3 and 6.

FIG. 14 is a functional schematic detailing the generalized electrical circuit of the second type of performance assessment illustrated in FIGS. 4 and 7.

FIG. 15 is a block diagram depicting a generalized self-organizing control system consisting of a controlled plant involving multiple variables and of a plurality of the PSV conditioning'logic stages of FIG. 2 in conjunction with the performance assessment stage of FIG. 3.

Referring to the drawings, FIG. 1 diagrammatically illustrates a typical self-organizing control system which employs novel and improved PSV conditioning logic and performance assessment stages constructed in accordance with the present invention. The system illustrated is a closed-loop system consisting of the controlled plant 12 driven by the control signal on channel 21 [;L(t)] which is generated by the self-organizing control subsystem 11 based on the system error signal on channel 19 [e(t)] which is formed by a conventional differential amplifier 14 operating on the command input signal on channel 17 and a feedback signal on channel 18 which is produced by a sensor 13 monitoring the plant controlled variable on channel 22. The self-organizing control subsystem 11 consists of the performance assessment stage 15 (to be fully described later) which develops a reward-punish signal (V) on' on channel 21 [p.(t)] in response to the reward-.

punish signal on channel 20 and an internally stored history of past directions of change in the p.(t) control signal on channel 21. The characteristics of the Mt) control signal on channel 21 furnished to the plant 12 by the self-organizing control subsystem II are such as to achieve and maintain a minimum (ideally zero) system error signal on channel 19 regardless of arbitrary variations in the command signal input on channel 17 and variations in the controlled variable on channel 22 caused by changes within, or external disturbances acting upon the controlled plant 12.

Although the sensor 13 is illustrated as an external function in FIG. 1, it may obviously be incorporated as part of the controlled plant 12, in accordance with well-known practice, since its only requirement is to deliver to differential amplifier 14 a compatible feedback signal on channel 18 representing the state (controlled variable on channel 22) of controlled plant 12. Alternatively, the sensor 13 could be of the type which generates the error signal on channel 19 directly with the command input signal on channel 17 supplied to the sensor by suitable'electrical or other means, in accordance with well-known practice. In any event, the conventional differential amplifier 14 could be incorporated as part of the controlled plant 12, in accordance with standard practice, thereby reducing the required plant interface to the command input signal on channel 17, the system error signal on channel 19 to be delivered to the self-organizing control subsystem 11, and the resultant p.(t) control signal on channel 21 generated by control subsystem l I.

The simplest form of self-organizing control system is illustrated in FIG. 1, i.e., a plant requiring control of only a single variable. The novel and improved self-organizing control techniques described in this disclosure are as readily adaptable to a complex, multivariable plant requiring simultaneous control of many related (coupled) or unrelated variables. Dependent upon plant characteristics, a typical self-organizing subsystem as illustrated could be used to control each variable; or a form of self-organizing control subsystem consisting of a single performance assessment stage and several PSV conditioning logic stages could be used to control multiple variables; or a form of self-organizing control subsystem consisting of a single performance assessment stage and multiple PSV conditioning logic stages whose outputs are paralleled by means of a conventional summing amplifier could be used to provide very reliable control of one variable. An extremely useful characteristic of these novel and improved self-organizing control techniques when applied to a multivariable plant is the fact that specific details regarding intervariable coupling (i.e., the interaction or interdependency of variables) need not be known to the designer or user of the self-organizing control system.

It will be readily apparent that in a system such as illustrated in FIG. 1, a vital function to be performed is that of dynamic performance assessment. System performance must be evaluated periodically or continuously to reinforce properly the courses of action taken by the PSV conditioning logic in generating the plant control signal. Since the performance assessment function relates directly to the selected criterion against which system performance is measured, this function tends to be problem-specific, and the performance criterion type and prediction time constant must be selected with attention to the requirements of the specific plant to be controlled. This limitation obviates design of a universal performance assessment function but does not preclude development of broad types of performance assessment function, with each type allowing for some parameter (for example, time constant) adjustability to accommodate widely different plant characteristics. The two types of performance assessment stages illustrated in FIGS. 3 and 4, and described in detail later in this disclosure, are examples of such broad types of performance assessment function.

FIG. 3 diagrammatically depicts one type of performance assessment function developed as a part of the invention herein disclosed. The essential purpose of performance assessment stage A is to perform a continuous assessment of self-organizing control system performance as a function of the e(t) system error signal on channel 19 and to generate a V rewardpunish signal on channel 20 based upon this assessment. The criterion used in the type 1 performance assessment stage 15A for generating the V signal on channel 20 is based on a tangentially extrapolated predictive function of system error. The predicted system error signal on channel 55 (e,,) is calculated by a predictor function 49, and may be expressed as e, e(t) T(t); where e(t) is the instantaneous system error signal on channel 19 and T is the prediction interval (constant). Since the over-all goal of the system is to reduce e(t) to zero as rapidly as possible without overshoot (which could result in an oscillatory convergence of the error to zero), it is desirable to generate a V signal on channel 20 which produces maximum acceleration until the predicted error changes sign and then an exponential convergence to zero error. A V signal of the form sgn V minus sgn e, sgn 5,, produces this result. Qualitatively, this form of V signal rewards those PSV conditioning logic actions which accelerate e, toward zero and punishes those actions which accelerate e, away from zero, while establishing the desired terminal response along the line e T 0. In theory, a ternary V signal, where +l= reward, -l= punish, and 0 zero reinforcement, could be employed. In practice, satisfactory results are obtained with a binary V signal, as described in this disclosure, where +1 reward and 0 punish.

FIG. 3 details the basic functions performed by the type 1 performance assessment stage to generate the above form of V signal. A predictor function 49, incorporating a prediction interval control 54 for flexibility of application, operates on the e(t) system error signal on channel 19 to obtain the predicted system error signal e, on channel 55, which in turn is operated on by differentiators 51 to obtain its second derivative, 2,, the signal on channel 57. Sign detectors 50 and 52 monitor e, and 22}, respectively, to provide sgn e',,, the signal on channel 56, and sgn 3,, the signal on channel 58, which, when gated by the reward-punish logic 53, generate the binary V signal on channel 20.

The operations which comprise the type 1 performance assessment stage of FIG. 3 are illustrated in more detail in FIG. 6. The operation performed by the predictor 49 on the e(t) signal on channel 19 may be expressed approximately as the Laplace transform l Ts), which yields e,, (the signal on channel 55) e(t) Te(t), where T is that period of time selected by prediction interval control 54. The predicted error e, is then fed to differentiators 51, consisting of differentiator stages and 101 in series, to obtain its second derivative, 25,, the signal on channel 57. The e, signal on channel 55 is also processed by a zero-crossing detector 104 and an output buffer 105 (level changer to obtain logic-compatible signals), which comprise sign detector 50, to obtain sgn e the signal on channel 56. In like manner, 5,, the signal on channel 57, is processed by zero-crossing detector 102 and output buffer 103, comprising sign detector 52, to obtain sgn 22' the signal on channel 58. The two binary signals, sgn e, and sgn 'e',, are then operated on by reward-punish logic 53, which implements the function sgn V minus sgn e, sgn 'e',,, to provide the desired binary V signal on channel 20. The type 1 performance assessment stage 15A output may be expressed as the Boolean functions V= reward sgn e 'sgn 'e, U sgn e 'sgn 5,, when the output is a logical one, and

V= Punish sgn e 'sgn 'e', U s gTa-sgn E, when the output is a logical zero.

The generalized electrical circuit and the circuit interconnections of the type 1 performance assessment stage 15A of FIGS. 3 and 6 are detailed by the functional schematic of FIG. 13. Specific component values and supply voltages are not shown since they are unique to the characteristics of a given controlled plant and to the characteristics of the components (such as the operational amplifiers, logic gates, and transistors) used for hardware implementation of the functional schematic.

The predictor 49 operates on the e(t) signal on channel 19 approximately per the Laplace transform (l Ts) to obtain the e signal on channel 55 [e,, e(t) T(t)]. The prediction interval T is selected by prediction interval control 54. Conventional operational amplifier 174, capacitors CIA (or, in its place, ClB, ClC, or C1D) and C2, and resistors R1, R2, and R3 comprise a standard augmented differentiator with a double high frequency cutoff, whose output is the sum of the input and its first derivative, and whose input is relatively insensitive to high frequency noise. The ratio of resistors R3 and R2 establishes the amplification factor (unity in this case) applied by amplifier 174 to the e(t) signal on channel 19. The time constant formed by resistor R3 and capacitor CIA (or, in its place, ClB, C1C, or C1D) determined the prediction interval T. Resistor R1 connected to capacitor CIA (or, in its place, ClB, ClC, or C1D) limits the high frequency response of predictor 49, and capacitor C2 shunting resistor R3 doubles the amount of attenuation of input frequencies higher than this limit, with both effects combining to render predictor 49 insensitive to high frequency noise which could mask the'derivative output.

The predicted error signal e, on channel 55 is then fed to differentiator 100, a standard differentiator with double high frequency cutoff, which consists of conventional operational amplifier 175, capacitors C3 and C4, and resistors R4 and R5, to obtain the e, signal on channel 106. The period of differentiation is established by resistor R5 and capacitor C3, while resistor R4 and capacitor C4 provide the required attenuation of high frequency noise. An identical differentiator 101 in series, consisting of operational amplifier 176, capacitors C5 and C6, and resistors R6 and R7, provides the second derivative of predicted error, the 5,, signal on channel 57. Sign detector 50, consisting of zero-crossing detector 104 and output buffer 105, then operates on the e, signal on channel 55 to obtain the required binary sgn e, the signal on channel 56. Sign information is extracted from the e, signal on channel 55 byemitter-coupled clippers 181 and 182, and is then operated on by level changer 183 and shaper 184. In an identical manner, the e, signal on channel 57 is processed by sign detector 52, consisting of zero-crossing detector 102 and output buffer 103, to provide the sgn e signal on channel 58. Sign information is extracted by emitter-coupled clippers 177 and 178, and then transformed to the proper binary signal by level changer 179 and shaper 180.

The signs of the predicted error and its first derivative are then processed by reward-punish" logic 53 to form the binary V signal on channel 20. First, inverters 185 and 186 generate m and sgn 'e respectively. AND-gate 187 then forms the logical product sgn e,,-sgn ',and AND-gate 188 forms the logical product s-g1fisgn e',,. The balance of the exclusive-OR function is performed by OR-gate 189 which forms the logical sum of logical products, sgn e -sgn 'e, U W-sg'n defined as V, the type 1 performance assessment stage A output parameter, the signal on channel 20.

FIG. 4 diagrammatically illustrates a second type of performance assessment function developed as a part of the present invention. As in performance assessment stage 15A, the purpose of performance assessment stage 15B is to perform a continuous assessment of selforganizing control system performance as defined by the e( t) system error signal on channel 19 and to generate a V (reward-punish) signal on channel 20 based upon this assessment. The criterion used in the type I 1 performance assessment stage 158 also uses a tangentially extrapolated predictive function of system error. Starting with the expression used for V in the type 1 performance assessment stage 15A (V minus sgn e -sgn and making the restrictive assumption that sgn 'e', sgn we obtain the expression V minus sgn e,-sgn 14,, where e, e(t) T(t) and we define [LP as a predicted value of the plant control signal, ;1.,, kp.(t) T,;1(t). As in the type l performance assessment stage 15A, this form of V signal 20 rewards those PSV conditioning logic actions which accelerate e, toward zero, and punishes those actions which accelerate e, away from zero. In the type II performance assessment stage 158, V, the signal on channel 20, is implemented as a binary signal where a logical one indicates a reward decision and a logical zero indicates a punish decision. Predicted system error, the signal on channel 65, is calculated by a predictor function 59, and may be expressed as e, e(t) T(t), where e(t) is the instantaneous system error signal on channel 19 and T is the prediction interval constant selected by the prediction interval control 64. A similar predictor function 61, with a fixed prediction interval based on specific controlled plant 12 characteristics, operates on the p.(t) plant control signal on channel 21 to obtain a predicted value of the plant control signal, u the signal on channel 67. Sign detectors 60 and 62 monitor e, and p.,,,- respectively, to provide sgn e,,, the signal on channel 66, and sgn u the signal on channel 68, which, when gated by the rewardpunish logic 63, generate the binary V signal on channel 20.

The operations which comprise the type I I performance assessment stage of FIG. 4 are illustrated in greater detail in FIG. 7. The operation performed by the predictor 59 on the e(t) signal on channel 19 may be expressed approximately as the Laplace transform (1 Ts), which yields e, (the signal on channel 65) e(t) Te'(t), where Tis that period of time selected by prediction interval control 64. In like manner, the u(t) plant control signal on channel 21 is operated on by predictor 61 approximately per the Laplace transform (k T s) to obtain 1.1., (the signal on channel 67) kp.( t) mm), where k is a fixed gain, and T, is a fixed prediction interval and k and T are chosen such that sgn u sgn it unless u is at one of its limits, in which event sgn u sgn u. The e, signal on channel 65 is processed by a zero-crossing detector 107 and an output buffer 108 (level changer to obtain logic-compatible signals), which comprise sign detector 60, to obtain sgn e,,, the signal on channel 66. In an identical manner, t, the signal on channel 67, is processed by zero-crossing detector 109 and output buffer 110, comprising sign detector 62, to obtain sgn u the signal on channel 68. The two binary signals, sgn e, and sgn u are then operated on by reward-punish logic 63, which implements the function sgn V minus sgn e, sgn p to provide the desired binary V signal on channel 20. The type 1 1 performance assessment stage 15 B output may be expressed as the Boolean function V reward sgn e, sgn u, U sgn e sgn p when the output is a logical one, and

P sgn p sgn M U p' am, when the output is a logical zero.

The generalized electrical circuit and the circuit interconnections of the type 1 1 performance assessment stage 15B of FIGS. 4 and 7 are detailed by the functional schematic of FIG. 14. Specific component values and supply voltages are not shown since they are unique to the characteristics of a given controlled plant and to the characteristics of the components (such as the operational amplifiers, logic gates, and transistors) used for hardware implementation of the functional schematic.

The predictor 59 operates on the e(t) signal on channel 19 approximately per the Laplace transform l Ts to obtain the e, signal on channel 65 [e,,= e(t) T(t) The prediction interval T is selected by prediction interval control 64. Conventional operational amplifier 190, capacitors C7A (or, in its place, C7B, C7C, or C7D) and C8, and resistors R8, R9 and R10 comprise a standard augmented differentiator with a double high frequency cutoff, whose output is the sum of the input and its first derivative, and whose input is relatively insensitive to high frequency noise. The ratio of resistors R10 and R9 establishes the amplification factor (unity in this case) applied by amplifier 190 to the e(t) signal on channel 19. The time constant formed by resistor R10 and capacitor C7A (or, in its place, C7B, C7C, or C7D) determines the prediction interval T. Resistor R8 connected to capacitor C7A (or, in its place, C7B, C7C, or C7D) limits the high frequency response of predictor 59, and capacitor C8 shunting resistor R10 doubles the amount of attenuation of input frequencies higher than this limit, with both effects combining to render predictor 59 insensitive to high frequency noise which could mask the derivative output.

The operations performed by predictor 61 on the p.(t) signal on channel 21 are similar to the operations performed by predictor 59. The approximate Laplace transform (k T s) is implemented by predictor 61 to obtain the ;1.,, signal on channel 67 [u kp,(t) T (t)]. Conventional operational amplifier 195, capacitors C9 and C10, and resistors R11, R12, and R13 comprise a standard augmented differentiator with a double high frequency cutoff, whose output is the sum of the input and its first derivative, and whose input is relatively insensitive to high frequency noise. The ratio of resistors R13 and R12 establishes the amplification factor k applied by amplifier 195 to the p.(t) signal on channel 21. The time constant formed by resistor R13 and capacitor C9 specifies the prediction interval T Resistor R1 1 connected to capacitor C9 limits the high frequency response of predictor 61, and capacitor C10 shunting resistor R13 doubles the amount of attenuation of input frequencies higher than this limit, with both effects combining to render predictor 61 insensitive to high frequency noise which could mask the derivative output.

The predicted error signal e, (the signal on channel 65) is then operated on by sign detector 60, consisting of zero-crossing detector 107 and output buffer 108, to

obtain the required binary sgn e,, the signal on channel 66. Sign information is extracted from e,,, the signal on channel 65, by emitterrcoupled clippers 191 and 192, and is then operated on by level changer 193 and shaper 194. In an identical manner, u the signal on channel 67, is processed by sign detector 62, consisting of zero-crossing detector 109 and output buffer 1 10, to

provide sgn 1., the signal on channel 68. Sign information is extracted by emitter-coupled clippers 196 and 197, and then transformed to the proper binary signal by level changer 198 and shaper 199.

The signs of the predicted system error and the we dicted value of the plant control signal are then processed by reward-punish" logic 63 to form the binary V signal on channel 20. First, inverters 200 and 201 generate sgTej, and sgn u respectively. AND-gate 202 then forms the logical product sgn e, Wand AND-gate 203 forms the logical product sg n"ej' sgn u The balance of the exclusive-OR function is performed by OR-gate 204 which forms the logical sum of logical products sgn e, 557,, U m sgn u defined as V, the type 11 performance assessment stage 15B output parameter, the signal on channel 20.

It is apparent from the foregoing descriptions that the type 1 performance assessment stage 15 A of FIGS. 3 and 6 and the type 1 1 performance assessment stage 15B of FIGS. 4 and 7 perform the same basic functions of continuous assessment of self-organizing control system performance based on the system error signal, e(t), and both generate a reward-punish signal, V, based upon this assessment. Further, both types of performance assessment stage use a predictive function of system error. This predictive function need not consist of the simple tangential extrapolation described above but may employ nonlinear or higher-order linear prediction. However, tangential extrapolation, which is theoretically optimum for linear, second-order controlled plants, is adequate for linear plants of higher than second order and many nonlinear plants.

The dissimilarities between the type 1 and type 11 performance assessment stages lie in the criteria employed to generate their respective V signals, and in the resultant dependence upon, or independence of, certain characteristics of the specific controlled plant. In review, the criterion upon which Type 1 performance assessment stage 15A bases its V signal is sgn v minus sgn e, sgn 5,, in which the sign of the predicted error is coordinated with the sign of the acceleration of predicted error. If the latter has the opposite sign from the former, a reward signal level is generated by stage 15A and sent to the PSV conditioning logic stage 16. Conversely, if the signs of the predicted error and the acceleration of predicted error are the same, a punish signal level is generated by stage 15A to guide the PSV conditioning logic. The PSV conditioning logic stage 16 then determines which direction of the plant control signal on channel 21 produced the particular reward or punish assessment. It is therefore immaterial, for this configuration of self-organizing control system, whether the controlled plant polarity a' lau is positive or negative: the type 1 performance assessment stage 15A working in conjunction with the PSV conditioning logic stage 16 will experimentally determine this information.

As explained earlier, the type 1 1 performance assessment stage 153 bases its V signal upon the criterion sgn v minus sgn e 'sgn p.,,. This criterion was developed by making the restrictive assumption that sgn E, sgn u where u, kp.(t) T, int). The sign of the predicted system error is now coordinated in a fixed way with the sign of an extrapolated value of the plant control signal, p.(t), with an immediate advantage of less sensitive circuitry required for hardware implementation, due to elimination of differentiators 100 and 101 (FIG. 13). As in the type 1 performance assessment, a reward signal level is generated by stage 158 if the signs of e, and u, are dissimilar and a punish signal level is generated if the signs of e, and u are identical. The lack of sign information for predicted error acceleration requires that the controlled plant polarity (15,/a be known a priori, as this configuration of the self-organizing control system cannot determine plant polarity through experimentation. (For the purpose of this development, plant polarity was assumed to be negative; a positive polarity would require that the V signal on channel 20 be complemented.) This disadvantage is more than offset for many applications by the absence of the term in the performance assessment criterion, making operation of the self-organizing control system much less sensitive to environmental and sensor noise and to the order of the controlled plant.

As illustrated in FIG. 1, the V(r eward-punish) signal on channel 20 generated by performance assessment stage 15 is supplied to the PSV conditioning logic stage 16. In turn, PSV conditioning logic stage 16 utilizes the V signal on channel and an internally stored history of directions of change of the p.(t) plant control signal on channel 21 to increment the p.(t) signal on channel 21. The direction of the increment of the p.(t signal on channel 21 supplied to the controlled plant 12 by the self-organizing control subsystem 11 is that direction which will minimize the e(t) system error signal on channel 19, resulting from a comparison of the command input signal on channel 17 and the sensed signal on channel 18 which represents the controlled plant output variable on channel 22. In brief, the PSV conditioning logic stage 16 functions as a signal generator whose output signal magnitude and sign are based on a continuous dynamic assessment of actual plant performance versus desired plant performance. The successful accomplishment of this function by the PSV conditioning logic stage 16 is due to its ability to associate cause and effect, basing its decisions on accumulated evidence concerning the present or predicted results of its past actions, thereby permitting realization of effective control even though characteristics of the controlled plant are incompletely known to the control system designer and user.

FIG. 2 diagrammatically defines the functions comprising the PSV conditioning logic stage developed as a part of the present invention. The PSV conditioning logic stage 16 consists of: a U register 28 which, with its associated control logic 27 and digital-to-analog (D/A) converter 29, increments, stores, converts, and buffer amplifies the p.(t plant control signal appearing on channel 21; a statistical source 26, whose probabilistically biased random noise output signal on channel 38 controls the incrementation of the U register 28; a P register 24, which, with itsassociated control logic 23 and digital-to-analog (D/A) converter 25, generates the probability control voltage, v, the signal on channel 37, that controls the probability of the statistical source output signal on channel 38 being at the logical one or logical zero level; a sign Ap.(t memory 30, which stores the directions of change in the Mt plant control signal on channel 21 and provides the sgn An signal on channel 48 that, in conjunction with the V signal on channel 20 from a performance assessment stage 15, determines the direction of incrementation of the P register 24; and a logic time base 31, whose function is to generate the clock pulses (C1, the signal on channel 43; C2, the signal on channel 44; C3, the signal on channel 45; C4, the signal on channel 46; and C5, the signal on channel 47) which control the sequence of events associated with each increment of the p.(r control signal on channel 21. In summation, the operation of the PSV conditioning logic stage 16 is such that the probabilities associated with alternative directions of change of the output variable, (t which is the plant control signal on channel 21, are biased in favor of changes which produced desirable results, as indicated by the state of the V signal on channel 20 as generated by the performance assessment stage 15. The sequence of major events occurring during each sample period is: (l the P register 24 is incremented, thus changing the output statistics of the statistical source 26, (2 the U register 28 is incremented in accordance with he new probabilities, and (3 the direction of the U register 28 increment is stored in the sign Ap.(t memory 30.

The operations which comprise the PSV conditioning logic stage of FIG. 2 are illustrated in greater detail in FIG. 5. The P-register control. logic 23, consisting of add-subtract decision logic 69 and decision memory 70, generates the ADD signal on channel 34 and the SUBTRACT signal on channel 35, which determine the direction of the increment of P register 24. Add-subtract decision logic 69 correlates the V signal on channel 20 from the performance assessment stage 15 with the sgn Ap. signal -on channel 48 representing the change in the ,u.(t) signal on channel 21 which resulted in the reward punish" decision. The form of this correlation is such that a positive increment to the P-register 24 contents is ordered if the V signal on channel 20 indicates a reward and the sgn Au signal on channel 48 indicates the associated change in the p.(t) signal on channel 21 was a positive increment, or if the V signal on channel 20 indicates a punish and the sgn Au signal on channel 48 indicates the associated change in the p (t) signal on channel 21 was a negative incremenLConversely, a negative increment to the P- register 24 contents is ordered if the V signal on channel 20 indicates a reward and the sgn Ap. signal on channel 48 indicates the associated change in the p.(t) signal on channel 21 was a negative increment, or if The V signal on channel 20 indicates a punish and the sgn Ap. signal on channel 48 indicates the associated change in the ;:.(t) signal on channel 21 was a positive increment. At the occurrence of clock pulse C1, the signal on channel 43 generated by the logic time base 31, the decision of add-subtract logic 69 is stored in decision memory 70, which provides the ADD signal on channel 34 and the subtract signal on channel 35 to the P register 24. These P-register control signals are described by the Boolean functions ADD= V-sgn Ap. U V-sgn Ag. and

The P register 24 consists of counter up-down steering logic 71 and a three-stage reversible counter 72. the function implemented by P register 24 is that of a standard three-bit binary up-down counter, with seven of the eight possible counter states utilized. Limit gates within counter up-down steering logic 71 monitor the contents of the three-stage reversible counter 72 and detect the counts of one and seven. The counter updown steering logic 71 senses the level of the ADD signal on channel 34 and the SUBTRACT signal on channel 35 at the occurrence of the clock pulse C2, the signal on channel 44 generated by the logic time base 31, and generates a COUNT-UP signal on channel 90 if the ADD signal on channel 34 is true and a count of seven is not detected in the three-stage reversible counter 72. Conversely, a COUNT-DOWN signal on channel 91 is generated if the SUBTRACT signal on channel 35 is true and a count of one is not detected in the three-stage reversible counter 72. If the threestage reversible counter 72 is in either the one state or the seven state, it remains in the state until a true ADD signal on channel 34 or a true SUBTRACT signal on channel 35, respectively, is sensed at the time of occurrence of the C2 signal on channel 44. The COUNT-UP signal on channel 90 is thus described by the Boolean function UP ADD-CNT 7-C2 while the COUNT-DOWN signal 91 is described by DOWN SUB-CNT 1-C2.

The contents of P register 24, the signal on channel 36, are processed by D/A converter 25 to generate v,,, the signal on channel 37, which in turn controls the probability of the statistical'source (SS) 26 output,

which is the signal on channel 38, being in the logical one state or the logical zero state. A count of four in P register 24 results in a 50 percent probability that the SS output signal on channel 38 will be in the logical one state at any given instant of time, while a count of seven results in approximately a 95 percent probability that the SS output signal on channel 38 will be in the logical one state and a count of one results in approximately a 5 percent probability that the SS output signal on channel 38 will be in the logical one state. Intermediate counts in P register 24 result in intermediate probabilities for a logical one state or a logical zero state to occur at the SS output at any given instant of time. Although an approximately linear relationship between the contents of P register 24 and the probability of the SS output signal on channel 38 being in the logical one state was implemented in the invention herein described, a linear relationship is not required. The operation of PSV conditioning logic l6 and the self-organizing control system could be improved by appropriate nonlinearities in the relationship, although the benefits from this are slight. The chief restriction is that any positive increment in P-register 24 contents must result in an increase in probability of a logical one state and any negative increment in P-register contents must result in a decrease in probability of a logical one state.

The D/A converter 25 consists of precision bitweight resistors 73 and operational amplifier 74. The actual D/A conversion is performed by precision bitweight resistors 73, which comprise a standard resistive summation network. One end of a precision resistor is connected to the true output of each counter stage of the P register 24, and the other ends of the resistors are tied in common, forming a summation point. Since the value of each of the precision resistors differs from the value of adjacent resistors by a power of two, with the lowest value connected to the most significant bit and the highest value connected to the least significant bit of P register 24, the summation point provides an analog voltage level, the signal on channel 92, that accuratelyrepresents the contents of P register 24. This analog voltage level is then amplified by operational amplifier 74 to provide the bipolar probability control voltage, v,,, the signal on channel 37, applied to the statistical source 26.

Basically, the statistical source 26 is a signal generator whose output, n,(p), the signal on channel 38, is a probabilistically biased random sequence of logical ones and logical zeroes. The statistical source consists of a random noise generator 76, a threshold comparator 75, and an output buffer 77. The random noise generator 76 generates a random noise output, n,, the signal on channel 93, with an approximately Gaussian distribution. The threshold comparator then compares the random noise signal, 11,, on channel 93, with the probability control voltage, v,,, the signal on channel 37, to generate a random binary sequence having a duty cycle (ratio of the number of logical ones to logical zeroes occurring over a statistically meaningful period of time) which is in direction proportion to the magnitude and polarity of v,,, the signal on channel 37. A probability control voltage of zero (P-register 24 contents equal four) results in a duty cycle of approximately 50 percent, while a maximum negative voltage (P-register 24 contents equal seven) results in a duty cycle of approximately percent and a maximum positive voltage (P-register 24 contents equal one) results in a duty cycle of approximately 5 percent. An output buffer 77 then transforms this probabilistically biased signal to levels compatible with the logic gates of the U-register control logic 27, thereby providing the statistical source output, n,(p), the signal on channel 38, and a maximum positive voltage (P-register 24 contents equal one) results in a duty cycle of approximately 5 percent. An output buffer 77 then transforms this probabilistically biased signal to levels compatible with the logic gates of the U-register control logic 27, thereby providing the statistical source output, n,,( p), the signal on channel 38, which consists of a random sequence of logical ones and logical zeroes with a probabilistically controlled duty cycle.

The U-register control logic 27, consisting of addsubtract decision logic and memory 78, generates an ADD signal on channel 39 and a SUBTRACT signal on channel 40 which determine the direction of each increment of U-register 28 contents. The add-subtract decisions are based chiefly upon the instantaneous state of mp), the signal on channel 38. At the occurrence of clock pulse C3, the signal on channel 45 generated by the logic time base 31, the state of the n,( p) signal on channel 38 is sampled, and the resultant add or subtract decision is stored in a short-term decision memory. The ADD signal on channel 39 is in the true state if the n,(p) signal on channel 38 was a logical one, and the SUBTRACT signal on channel 40 is in the true state if the n,(p) signal on channel 38 was a logical zero. Thus, it is seen that the direction on the U- register 28 increment is random, with a statistical bias dependent upon the instantaneous state of statistical source 26. That is, the probability of a positive or a negative increment of U-register 28 contents is a function of the probability control voltage, the signal on channel 37.

The U register 28 consists of counter up-down steering logic 79 and a four-stage reversible counter 80. The function implemented by U register 28 is that of a standard four-bit binary down counter, with 15 of the 16 possible counter states utilized. Limit gates within counter up-down steering logic 79 monitor the contents of four-stage reversible counter 80 and detect the counts of one and 15. The counter up-down steering logic 79 senses the levels of the ADD signal on channel 39 and the SUBTRACT signal on channel 40 at the occurrence of clock pulse C4, the signal on channel 46 generated by the logic time base 31, and generates a COUNT-UP signal on channel 94 if the ADD signal on channel 39 is true and if a count of 15 is not detected in the four-stage reversible counter 80. Conversely, a COUNT-DOWN signal on channel 95 is generated if the SUBTRACT signal on channel 40 is true" and if a count of one is not detected in the four-stage reversible counter 80. If the four-stage reversible counter 80 is in either the one state or the 15 state, it remains in that state until a true ADD signal on channel 39 or a true SUBTRACT signal on channel 40, respectively, is sensed at the time of occurrence of C4, the signal on channel 46. The COUNT-UP signal on channel 94 is described by the Boolean function UP ADD-CNT l5-C4 while the COUNT-DOWN signal on channel 95 is described by DOWN SUB'CNT l-C4.

The contents of U register 28, the signal on channel 41, are processed by D/A converter 29 to generate the p.(t) plant control signal on channel 21 and its inverse, the ;;,(t) signal on channel 42. The ;.:,(t) signal on channel 21 is fed directly to the controlled plate 12, and both the p,(t) signal on channel 21 and the p.(t) signal on channel 42 are used by the sign Ap.(t) memory 30 to derive the direction of change of the p.(t) plant control signal on channel 21, which is then stored for subsequent use in determining required changes in the control system statistical bias. The D/A converter 29 consists of precision bit-weight resistors 81 and inverting operational amplifiers 82 and 83. The actual D/A conversion is performed by precision bitweight resistors 81, which comprise a standard resistive summation network. One end of a precision resistor is connected to the true output of each counter stage of the U register 28, and the other ends of the resistors are tied in common, forming a summation point. Since the value of each of the precision resistors differs from the value of adjacent resistors by a power of two, with the lowest value connected to the most significant bit and the highest value connected to the least significant bit of U register 28, the summation point provides an analog voltage level, the signal on channel 96, that accurately represents the contents of U register 28. This analog voltage level is then amplified by inverting operational amplifier 82 to provide the bipolar plant control signal, p.(t the signal on channel 21. Another inverting operational amplifier 83 in series operates on the Mt) signal on channel 21 with a unity amplification factor to provide the inverse signal, -;t(t) the signal on channel 42.

The sign Apt(t) memory 30, consisting of slope detectors 84 and 85, sgn Ap. temporary memory 86, and four-stage shift register 87, monitors the [L(t) signal on channel 21 and the p.(t signal on channel 42 to determine the current direction of the increment, if any, of U-register 28 contents and then stores the direction of the increment, sgn A;:., the signal on channel 48, in a register that always contains the direction of the four most recent increments. The slope detector 84 monitors the ,u(! signal on channel 21 and detects a positive transition in the signal to generate a pulse, the signal on channel 97, which indicates the current sgnAu was positive. In a like manner, slope detector 85 monitors the p.(t) signal on channel 42 (the inverse of the p.(t) signal on channel 21) and detects a positive transition in the signal to generate a pulse, the signal on channel 98, which indicates the current sgn Ap, was negative. The pulse appearing on channel 97 or 98, indicating that sgn Ap. was positive or negative, respectively, sets or resets sgn AIL temporary memory 86. Then, at the occurrence of clock pulse C5, the signal on channel 47 generated by the logictime base 31, the sgn Ap information in sgn Au temporary memory 86 is transferred to a four-stage shift register 87. At the beginning of any sample period t, the four-stage shift register 87 contains, in stages 1 4, the sgn Ap. information for sample periods I l, t 3, t 3, and t 4, respectively. The sgn All. delay select 32 determines from which register stage the sgn Au signal on channel 48 is obtained; i.e., to which prior sample period the sgn Ap. information pertains. In this disclosure, a sgn Ap. signal on channel 48 equal to logical one indicates a positive increment in the p,(t) signal on channel 21, and a sgn Ap. signal on channel 48 equal to logical zero indicates a negative increment in the p.(t) signal on channel 21.

The proper sequence of events within each sample period is maintained by the logic time base 31, which generates clock pulses C1, the signal on channel 43; C2, the signal on channel 44; and C5, the signal on channel 47. A standard transistor oscillator 88 establishes the sample period repetition rate which may be varied by the sample rate control 33. The output signal on channel 99 of the oscillator 88 is delayed by varied amounts and shaped by the clock pulse delay and shaping network 89 to generate the sequential clock pulses. Although the logic time base described in this disclosure generates sample periods occurring at regular intervals of time, the self-organizing control system of this invention could as well incorporate an aperiodic or random logic time base, without regular time-spacing of sample periods and without set time intervals between the clock pulses in any given sample period. The only requirement is to provide C1, the signal on channel 43; C2, the signal on channel 44; C3, the signal on channel 45; C4, the signal on channel 46; and C5, the signal on channel 47, in the proper sequence as described in this disclosure.

The generalized electrical circuits and the circuit interconnections of the PSV conditioning logic 16 of FIGS. 2 and 5 are detailed by the functional schematics of FIGS. 8 through 12. Specific component values and supply voltages are not shown since they are unique to the characteristics of a given controlled plant and to the characteristics of the components (such as the operational amplifiers, logic gates, and transistors) 

1. In a self-organizing control system, a controlled device provided with means developing system performance signals corresponding to the state of the device and having an input adapted to receive a regulating control signal, means to generate said regulating control signal comprising an input signal combining device adapted to receive a command signal, feedback means connecting said system performance signal developing means to said combining device, whereby said combining device provides an output signal representing system error, a performance assessment device for comparing the sign of a predicted error signal and a second variable signal to develop a ''''rewardpunish'''' output signal in accordance with information received thereby, means connecting the output of the combining device to the input of the performance assessment device, conditioning logic means for providing output signals in accordance with the combination of a prevailing input signal thereto and a previous output signal thereof, means connecting the output of the performance assessment device to the input of the conditioning logic means and means for coupling the output of said conditioning logic means to the input of said controlled device, wherein saiD conditioning logic means includes a plurality of conditioning logic devices, each connected to said performance assessment device and each developing an output signal in accordance with the combination of a prevailing input signal thereto and a prior output signal thereof, and means responsive to a sub-plurality of said conditioning logic devices for providing one of a plurality of regulating control signals.
 2. A system as set forth in claim 1 wherein said second variable signal is a derivative of said predicted error signal.
 3. A system as set forth in claim 1 wherein said second variable signal is a predicted control signal.
 4. A system as set forth in claim 1 further including summing means connected to each of said subplurality of said conditioning logic devices for summing the outputs of said subplurality of said conditioning logic devices for providing one of said plurality of regulating control signals.
 5. A system as set forth in claim 1 further including second means responsive to a second subplurality of said conditioning logic devices for providing a second of said plurality of regulating control signals.
 6. A system as set forth in claim 4 further including second means responsive to a second subplurality of said conditioning logic devices for providing a second of said plurality of regulating control signals.
 7. A system as set forth in claim 1 wherein said feedback means includes a plurality of feedback paths.
 8. A system as set forth in claim 1 wherein said feedback means includes a plurality of feedback paths.
 9. A system as set forth in claim 1 further including a plurality of actuators in said controlled device, controlled by said output signals from said conditioning logic means, said feedback means including a plurality of feedback paths, each feedback path coupled to a different one of said actuators.
 10. A system as set forth in claim 9 wherein said conditioning logic means includes a plurality of conditioning logic devices, each connected to said performance assessment device and each developing an output psignal in accordance with the combination of a prevailing input signal thereto and a prior output signal thereof, and means responsive to a subplurality of said conditioning logic devices for providing one of a plurality of regulating control signals.
 11. A system as set forth in claim 10 further including summing means connected to each of said subplurality of said conditioning logic devices for summing the outputs of said subplurality of said conditioning logic devices for providing one of said plurality of regulating control signals.
 12. A system as set forth in claim 11 wherein said actuators are each controlled by one of said plurality of regulating control signals.
 13. A system as set forth in claim 1 wherein said input combining device includes a first combining device for providing a signal indication of the difference between a first input command signal and an input signal from said feedback means, a second combining device for providing a signal indication of the difference between a second input command signal and and input signal from said feedback means and means for combining said difference signals.
 14. A system as set forth in claim 13 wherein said feedback means includes a plurality of feedback paths, each feedback path coupled to a different one of said first and second combining devices.
 15. A system as set forth in claim 14 further including individual means responsive to each of said signals indicative of difference for providing the absolute value of said difference.
 16. A system as set forth in claim 15 further including means for weighting said signals indicative of absolute value prior to combination thereof.
 17. A system as set forth in claim 15 wherein said conditioning logic means includes a plurality of conditioning logic devices, each connected to said performance assessment device and each developing an output signal in accordance with the combination of a prevailing iNput signal thereto and a prior output signal thereof, and means responsive to a subplurality of said conditioning logic devices for providing one of a plurality of regulating control signals.
 18. A system as set forth in claim 17 further including summing means connected to each of said subplurality of said conditioning logic devices for summing the outputs of said subplurality of said conditioning logic devices for providing one of said plurality of regulating control signals.
 19. A system as set forth in claim 13 wherein said conditioning logic means includes a plurality of conditioning logic devices, each connected to said performance assessment device and each developing an output signal in accordance with the combination of a prevailing input signal thereto and a prior output signal thereof, and means responsive to a subplurality of said conditioning logic devices for providing one of a plurality of regulating control signals.
 20. A system as set forth in claim 9 further including summing means connected to each of said subplurality of said conditioning logic devices for summing the outputs of said subplurality of said conditioning logic devices for providing one of said plurality of regulating control signals.
 21. A statistical decision device for low signal to noise ratio signals which comprises first means to provide an input signal having low signal to noise ratio, second means responsive to said signal for incrementally changing its state in response to said signal, a source of random signals and third means responsive to the state of said second means and said random signals for providing an output signal indicative of the polarity of said input signal.
 22. A statistical decision device as set forth in claim 21 wherein said second means includes a reversible counter responsive to said signal having low signal to noise ratio.
 23. A statistical decision device as set forth in claim 21 wherein said third means includes a comparator responsive to the state of said second means for providing a reference to determine the polarity of said random noise signal.
 24. A statistical decision device as set forth in claim 22 wherein said third means includes a comparator responsive to the state of said second means for providing a reference to determine the polarity of said random noise signal.
 25. A statistical decision device as set forth in claim 21 wherein said signal having low signal to noise ratio is digital and means coupling said second means and said third means for converting said digital signal to an analog signal whereby the state of said second means is represented by an analog signal.
 26. A statistical decision device as set forth in claim 24 wherein said signal having low signal-to-noise ratio is digital and means coupling said second means and said third means for converting said digital signal to an analog signal whereby the state of said second means is represented by an analog signal. 